the 56858 offers a rich feature set and on-chip memory interface. it includes external memory expansion with up to 4 mb program or up to 16 mb data addressing space, and is available in both 144 lqfp and 144 mbga packages. the 56858 includes 80 kb of on-chip program sram and 48 kb of on-chip data sram. with two enhanced serial synchronous serial interfaces (essis), this device can provide outputs for 5.1-channel surround sound. the 56858 is ideal for client-side telecom/datacom applications requiring up to four channels, including ip phones. this device can be designed into multi-processor systems to provide internet audio and speech processing functionalities and can provide a stand-alone device for internet audio and automotive hands-free. jtag/eonce pll 16-bit quad timer up to 48 gpio cop/watchdog ext memory if (2) sci data memory 56800e core 120 mips 2 kb boot rom 80 kb ram program memory 48 kb ram prog chip selects time of day 6-channel dma (2) essi spi 8-bit host benefits ? easy to program with flexible application development tools ? supports multiple processor connections ? 16-bit quad timer module (with four external pins) that allows capture/compare functionality, and can be cascaded ? quad timer module can also be used for simple digital-to-analog conversion functionality ? enhanced synchronous serial interface with enhanced network and audio modes ?t ime of day for applications requiring clock display ? flexible 6-channel direct memory access (dma) allows both internal and external memory transfers with almost no cpu interruption ? serial peripheral interface with master and slave mode supporting connection to other processors or serial memory devices ?t wo enhanced synchronous serial interfaces with three transmitters per module provide support for 5.1 channel surround sound for audio applications 56858 16-bit digital signal processors ? 120 mips at 120mhz ? 80 kb program sram ? 48 kb data sram ?2 kb boot rom ? access up to 2m words of program memory or up to 8m data memory ? chip select logic for glueless interface to rom and sram ? six independent channels of dma ?t wo enhanced synchronous serial interfaces (essi) ?t wo serial communication interfaces (sci) ? serial peripheral interface (spi) ? 8-bit parallel host interface ? general purpose 16-bit quad timer ?j t ag/enhanced on-chip emulation (once ? ) for unobtrusive, real-time debugging ? computer operating properly (cop)/watchdog timer ?t ime of day (tod) ? 144-pin lqfp and 144 mapbga packages ? up to 47 gpio energy information ? fabricated in high-density cmos with 3.3v, ttl-compatible digital inputs ?w ait and stop modes available t arget applications hybrid mcu/dsp 56858 120 mips hybrid processor ? full duplex feature phones ? ip phones ? client-side ip applications ? iads ?v oice and audio processing ?v oice recognition and command ? general purpose devices ? automotive hands-free
motorola and the stylized m logo are registered in the u.s. patent and trademark office. this product incorporates superflash ? technology licensed from sst. all other product or service names are the property of their respective owners. ? motorola, inc. 2003 ds p 56858 p b /d rev 5 ordering information aw ard-winning development environment ? processor expert? (pe) technology provides a rapid application design (rad) tool that combines easy-to-use component-based software application creation with an expert knowledge system. ? the codewarrior? integrated development environment (ide) is a sophisticated tool for code navigation, compiling and debugging. a comprehensive set of evaluation modules (evms) and development system cards will support concurrent engineering. together, pe, the codewarrior tool suite and evms create a comprehensive, scalable tools solution for easy, fast and efficient development. hybrid mcu/dsp 56858 product documentation 56858 peripheral circuit features ? general purpose 16-bit quad timer* ?t wo serial communication interfaces (sci)* ? serial peripheral interface (spi) port* ?t wo enhanced synchronous serial interface (essi) modules* ? computer operating properly (cop)/watchdog timer ?jt ag/enhanced on-chip emulation (once) for unobtrusive, real-time debugging ? six independent channels of dma ? 8-bit parallel host interface* ?t ime of day (tod) ? 144-pin lqfp and 144 mbga packages ? up to 47 gpio * each peripheral i/o can be used alternately as a general purpose i/o 56858 memory features ? harvard architecture permits up to three simultaneous accesses to program and data memory ? on-chip memory C 80 kb program ram C 48 kb data ram C2 kb boot rom ? off-chip memory expansion (emi) C access up to 4 mb program or up to 16 mb data memory (using chip selects) C chip select logic for glueless interface to rom and sram 56800e core features ? efficient 16-bit hybrid controller engine with dual harvard architecture ? 120 million instructions per second (mips) at 120mhz core frequency ? single-cycle 16 x 16-bit parallel multiplier-accumulator (mac) ? four 36-bit accumulators, including extension bits ? 16-bit bidirectional shifter ? parallel instruction set with unique addressing modes ? hardware do and rep loops ? three internal address buses and one external address bus ? four internal data buses and one external data bus ? instruction set supports both dsp and controller functions ? four hardware interrupt levels ? five software interrupt levels ? controller-style addressing modes and instructions for compact code ? efficient c compiler and local variable support ? software subroutine and interrupt stack with depth limited only by memory ?jt ag/enhanced once debug programming interface the 56800e core is based on a harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. the microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both dsp and mcu applications. the instruction set is also highly efficient for c compilers, enabling rapid development of optimized control applications. features of the 56800e core include: dsp56800e detailed description of the 56800e reference manual architecture, 16-bit dsp core processor and the instruction set order number: dsp56800erm/d dsp5685x detailed description of memory, users manual peripherals, and interfaces of the 56853, 56854, 56855, 56857, and 56858 order number: dsp5685xum/d dsp56858 electrical and timing specifications, t echnical data pin descriptions, and package sheet descriptions order number: dsp56858/d dsp56858 summary description and block diagram product brief of the core, memory, peripherals and interfaces order number: dsp56858pb/d p art supply p ackage type pin count frequency order number voltage (mhz) dsp56858 1.8v, 3.3v low-profile quad flat pack (lqfp) 144 120 dsp56858fv120 dsp56858 1.8v, 3.3v map ball grid array (mapbga) 144 120 dsp56858vf120 dsp56858 1.8v, 3.3v low-profile quad flat pack (lqfp) 144 120 spak56858fv120 dsp56858 1.8v, 3.3v map ball grid array (mapbga) 144 120 spak56858vf120
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